Our main research topic is the practical application of logic and formal methods for the specification and verification of software. In particular, we address the following application areas:
We offer a wide range of new topics for master and bachelor theses in areas such as verification of PLCs, extension of the KeY verification approach, formalisation/verification of social choice properties, and much more. Besides the advertised topics, we are open to your ideas within our research fields. If you are interested, please contact the corresponding members of our group.